FIGS. 4(a) to 4(k) are cross-sectional views illustrating process steps in a method for fabricating a prior art HEMT (High Electron Mobility Transistor) disclosed in, for example, Japanese Published Patent Application No. 63-174374 and Electronics Letters 24, 1988, p.1327.
Initially, a GaAs buffer layer 21, an intrinsic type (hereinafter referred to as i type) GaAs layer 22, an n type AlGaAs layer 23, and an n.sup.+ type GaAs layer 24 are successively grown on a semi-insulating GaAs substrate (not shown) by epitaxial growth. Then, an SiO.sub.2 film is deposited on the substrate to a thickness of about 3000 angstroms, forming a first insulating film 25. Then, a resist pattern 27 having an aperture of 0.5 micron width is formed on the first insulating film 25 (FIG. 4(a)).
Then, as illustrated in FIG. 4(b), the first insulating film 25 is etched using the first resist pattern 27 as a mask to form a first aperture 25a. Preferably, the first insulating film 25 is etched by dry etching using a mixture of CHF.sub.3 and O.sub.2 or CF.sub.4 and O.sub.2. Then, using the resist pattern 27 and the first insulating film 25 as a mask, the n.sup.+ type GaAs layer 24 is etched to form a recess 24a having a depth of about 1000 angstroms. Preferably, the GaAs layer 24 is etched by reactive ion etching using CCl.sub.2 F.sub.2 or by wet etching using a mixture of tartaric acid and hydrogen peroxide as an etchant (FIG. 4(c)). In FIG. 4(c), although the n.sup.+ type GaAs layer 24 is etched to expose the surface of the n type AlGaAs layer 23, the etching may be stopped in the n.sup.+ type GaAs layer 24.
After removing the resist pattern 27 using O.sub.2 ashing or an organic solvent as shown in FIG. 4(d), an SiO.sub.2 film is deposited on the n type AlGaAs layer 23 and the first insulating film 25 to a thickness of about 3000 angstroms, forming a second insulating film 28 (FIG. 4(e)). Preferably, the SiO.sub.2 film is deposited by plasma CVD.
Then, as illustrated in FIG. 4(f), the second insulating film 28 is etched in the perpendicular direction to the surface of the substrate by sputter etching or reactive ion etching, leaving portions at opposite sides of the first aperture 25a to form a second aperture 28a. The width w.sub.1 of the n type AlGaAs layer 23 exposed at the bottom of the second aperture 28a is about 0.25 micron.
Then, as illustrated in FIG. 4(g), a refractory metal 29, such as WSi, is deposited on the substrate to a thickness of 1500 angstroms by sputtering, followed by annealing. Then, a low resistance metal layer 30 comprising Ti 500 angstroms thick, Pt 1000 angstroms thick, and Au 3000 angstroms thick is formed on the refractory metal layer 29 by sputtering.
Then, a resist pattern 31 is formed on the low resistance metal layer 30. Using the resist pattern 31 as a mask, the low resistance metal layer 30 comprising Ti/Pt/Au is patterned by ion milling, and the refractory metal layer 29 comprising WSi and the insulating film 25 comprising SiO.sub.2 are patterned by reactive ion etching (FIG. 4(h)). During the etching process, the refractory metal layer 29 and the insulating film 25 are excessively etched, so that the width of the refractory metal layer 29 is narrower than the width of the low resistance metal layer 30. FIG. 4(i) illustrates a case where the etching rate of the reactive ion etching is further increased. In this case, the width of the refractory metal layer 29 is further decreased and the insulating film 25 is completely removed.
After removing the resist pattern 31 as shown in FIG. 4(j), a resist pattern for forming ohmic electrodes (not shown) is formed on the substrate, followed by a deposition of an ohmic electrode metal 32 comprising AuGe/Ni/Au and lift-off, resulting in a T-shaped gate electrode 33 and ohmic electrodes, i.e., source and drain electrodes 32a and 32b. Thereafter, the substrate is annealed at 400.degree. C. for two minutes to complete the HEMT of FIG. 4(k).
Since the insulating film 25 comprising SiO.sub.2 lying under the refractory metal layer 29 is completely removed in the step of FIG. 4(i), the gate-to-source capacitance (Cgs) is reduced. The insulating film 28 remaining on opposite sides of the lower part of the T-shaped gate electrode 33 protects the surface of the n type AlGaAs layer 23.
In the conventional HEMT, a region in which electrons travel, i.e., a region of the i type GaAs layer 22 where a two-dimensional electron gas is formed, is spaced apart from a region that supplies electrons, i.e., the n type AlGaAs layer 23, by the heterojunction to prevent the electrons from being scattered by donor impurities, whereby the electron mobility of the transistor is increased. In the HEMT, in order to increase the cut-off frequency (f.sub.t), the maximum oscillation frequency (f.sub.max), the unilateral gain (U) to reduce the noise factor (F.sub.0), it is necessary to reduce the gate length (Lg), the source resistance (Rs), the gate-to-source capacitance (Cgs), and the gate resistance (Rg).
In the conventional method for producing the HEMT illustrated in FIGS. 4(a)-4(k), since the gate electrode and the source and drain electrodes are formed self-alignedly, it is possible to reduce the gate length and the source resistance. In addition, since the gate electrode is formed in a T shape, the gate resistance is reduced to some extent.
In the steps of FIGS. 4(e) and 4(f), the second insulating film 28 is deposited on the substrate to fill the first aperture 25a and then etched away leaving portions on opposite side walls of the aperture 25a, which portions form a second aperture 28a having a width w.sub.1 of 0.25 micron that would be a gate length. Thereafter, the refractory metal 29 is deposited in the aperture 28a to form the lower part of the gate electrode. However, during etching the second insulating film 28, the first insulating film 25 is also etched and the thickness thereof is reduced, whereby, in the structure of FIG. 4(k), the interval between the over-hanging part 33a of the T-shaped gate electrode 33 and the surface of the n.sup.+ type GaAs layer 24 whereon the source and drain electrodes 32a and 33b are present is reduced, resulting in an increase in the gate-to-source capacitance.
Although it is thought that the above-described problem can be solved by increasing the thickness of the first insulating film 25, if the thickness of the first insulating film 25 increases, the etching precision when the aperture 25a is formed in the first insulating film 25 is reduced, and the aperture 25a is not completely filled with the second insulating film 28 when the insulating film 28 is deposited on the substrate. In this case, it is difficult to form the fine aperture 28a having a width w.sub.1 of about 0.25 micron with high controllability.
In the step of FIG. 4(f), the width w.sub.1 of the aperture 28a at the n type AlGaAs layer 23 varies according to the thickness of the second insulating film 28 deposited in the step of FIG. 4(e). More specifically, the width w.sub.1 decreases with an increase in the thickness of the second insulating film 28. When the second insulating film 28 is deposited to a thickness of 3000 angstroms as described above, the width w.sub.1 is about 0.25 micron. If the thickness of the second insulating film 28 is further increased to further reduce the gate length, the width of the V-shaped aperture 28a decreases. When the refractory metal 29 is deposited in the narrow V-shaped aperture 28a, the angle of the V-shaped groove 29a, shown in FIG. 5, formed opposite the V-shaped aperture 28a gradually decreases and the refractory metal 29 is not evenly deposited on the surface of the groove 28a, shown in FIG. 4(f). As a result, a void 30a, shown in FIG. 5, is formed in the low resistance metal layer 30 deposited on the refractory metal layer 29. That cavity increases the gate resistance.
Meanwhile, Japanese Published Patent Application No. 63-204772 proposes an improved method of forming a T-shaped gate structure, in which an upper metal layer of the T-shaped gate electrode is formed by plating using a lower metal layer of the gate electrode as a feeding electrode. In this plating method, however, it is difficult to apply ions to the uneven surface in the plating step, such as the surface with the V-shaped groove 29a, while keeping the ion concentration at the surface constant, so that it is impossible to deposit the upper metal layer free of voids.